1. Field of the Invention
The present invention relates to interfaces between a host computer and a peripheral device, such as a magnetic hard disk drive. More particularly, the present invention relates to a printed circuit assembly and to an integrated circuit including integrated resistors for terminating data and control lines of a host peripheral interface.
2. Description of the Prior Art and Related Information
Disk drives typically communicate with host computers via standardized interfaces. One such standardized interface is the Integrated Drive Electronics (IDE) interface, sometimes referred to as the AT attachment (ATA) interface. The IDE interface was originally based upon the IBM PC AT 16-bit bus standard, although most disk drives today utilize an enhanced version of the standard, which may be called EIDE or ATA-n where n represents a generation of the standard that has been documented in a standards committee. In the IDE or EIDE or ATA interfaces (hereafter collectively IDE), the disk drive controller is built into the logic board of the disk drive and communicates with the host computer system via a 40 conductor (typically flat) cable. Originally, programmed input/output (I/O) was used as the protocol for transferring data between the disk drive and the host computer system, forsaking the then slower Direct Memory Access (DMA) capabilities of the AT bus. The specification for the 40-conductor (unterminated) IDE interface called for seven ground wires and data signal transfer rate of about 6 to 8 MHz, the speed of the AT bus. While adequate for such low data transfer speeds, the programmed I/O method of data transfer, the low data transfer rate and the physical configuration of the IDE 40-conductor cable proved to be inadequate in the face of increasing drive performance and higher data transfer speed requirements.
The ATA interface, therefore, evolved over the years to allow high-speed DMA-based transfers. A new series of protocols, known variously as xe2x80x9cUltra-ATAxe2x80x9d, xe2x80x9cUltra DMAxe2x80x9d or xe2x80x9cUDMAxe2x80x9d have been developed to match increasing drive performance and higher data transfer rate requirements. Several UDMA xe2x80x9cmodesxe2x80x9d have been defined, each UDMA mode being a function of the nominal data transfer rate. For example, UDMA mode 0 specifies a nominal data transfer rate of 16.67 megabytes per second (hereafter MB/s). Mode 1 specifies a transfer rate of 22.22 MB/s, Mode 2 a transfer rate of 33.33 MB/s, Mode 3 a rate of 44.44 MB/s and mode 4, a nominal data transfer rate of 66.66 MB/s. Such high transfer rates were made possible by a number of modifications to the ATA bus, including the implementation of double-edged clocking, source-synchronous signaling and a series resistor termination at the interface to match the characteristic impedance of the cable. The series-terminating resistor reduces ringing and reflection of the signal propagated down the cable and allows a faster data settling time, a crucial and transfer speed-determinative measure.
For transfer speeds up to about 33.33 MB/s (UDMA modes 0-2), the original 40-conductor cable is adequate. However, as the 40-conductor cable only includes 7 ground wires (only two of which are adjacent to the data lines), crosstalk is a major factor in scaling up to data transfer rates above those specified in modes 0-2. For UDMA modes 3 and 4, therefore, a new 80-conductor cable has been developed that includes ground return paths alternating between each of the original 40 conductors. Each of the 40 ground wires of the 80-conductor cable is connected to the 7 ground wires of the original 40-conductor UDMA cable. The addition of the 40 ground wires decreases crosstalk and the inductance on the ATA bus. In scaling up to data transfer rates of 33.33 and 66.6 MB/s and beyond, the series termination takes on a critical importance, because the electrical characteristics of the source-terminated line ultimately determine what data rates are achievable. In the UDMA environment, the effective driving impedance of a source, as seen from the connector, should be between about 40 ohms (xcexa9) and about 50 xcexa9, for a series terminating resistor having the recommended value of about 33 xcexa9.
Typically, surface mounted resistors are used to terminate the ATA interface. Although surface mounted resistors are relatively inexpensive, their use in the ATA interface entails non-negligible assembly costs to mount the resistors on the printed circuit board of the interface. Moreover, surface mounted components, such as resistors, occasionally suffer from solder shorts, misconnections, and other physical defects. Therefore, costs must be allocated, during the interface manufacturing process, to identify and correct such defects.
Heated competition in the consumer and enterprise-level computer peripheral market has led disk drive manufacturers to trim costs wherever possible. The UDMA host interface has been identified as a potential candidate for the implementation of further cost-saving measures. Indeed, it is desirable to find cost-effective alternatives to surface-mounted series terminating resistors. Such alternatives should reduce the overall costs of the interface, including the material costs of the surface-mounted resistors themselves, as well as the accompanying costs of mounting the resistors on the board and the costs associated with identifying and correcting such physical defects at solder shorts and misconnections, while providing an effective termination of the interface, consistent with data transfer speeds having a magnitude at least as great as those specified in UDMA modes 3 and 4.
An object of this invention, therefore, is to provide cost-effective printed and integrated circuitry for host peripheral interfaces supporting the UDMA data transfer protocols and other high data transfer speed protocols. More particularly, an object of this invention is to provide a lower-cost alternative to surface mounted termination transistors for terminating data and control lines of a host-peripheral interface.
Accordingly, this invention can be regarded as a printed circuit board assembly (PCBA) that is plug compatible with a host-peripheral interface via which digital data are synchronously transmitted at a data rate via conductive paths that exhibit transmission-line characteristics at the data rate. The printed circuit board assembly comprises a first and a second integrated-circuit terminal and a first and a second connector terminal. The PCBA also includes a first transmission line for transmission of a data signal and a second transmission line for transmission of a clocking signal. Integrated circuitry on the PCBA includes a first and second pad, a first digital circuit for propagating the data signal through the first pad and a second digital circuit for propagating the clocking signal through the second pad. The first transmission line includes a first integrated-circuit conductive path including a first integrated-circuit resistive element connected in series between the first pad and the first digital circuit and a first printed-circuit conductive path. The second transmission line includes a second integrated-circuit conductive path including a second integrated-circuit resistive element and a second printed-circuit conductive path. The first integrated-circuit element has a first ohmic value and the second integrated-circuit element has a second ohmic value. The first printed circuit conductive path has a third ohmic value, and the second printed circuit conductive path has a fourth ohmic value. The ratio of the third ohmic value to the first ohmic value is such that the first ohmic value is in excess of an order of magnitude greater than the third ohmic value. The ratio of the fourth ohmic value to the second ohmic value is such that the second ohmic value is in excess of an order of magnitude greater than the fourth ohmic value. The ratio of the first ohmic value to the second ohmic value is substantially less than the ratio of the third ohmic value to the first ohmic value.
According to other embodiments, the first integrated resistive element may include one or more first n-type portions and one or more first p-type portions. The first n-type portion(s) may include material doped with an n-type dopant, and the first p-type portion(s) may include material doped with a p-type dopant, the first n-type portion(s) and the first p-type portion(s) being electrically coupled to one another via a first metal layer. The first n-type portion(s) may include a first n-type layer including material doped with the n-type dopant and a second n-type layer including material doped with the n-type dopant, the second n-type layer being electrically coupled to the first n-type layer by the first metal layer. The second integrated resistive element may include one or more second n-type portions and one or more second p-type portions, the second n-type portion(s) including material doped with an n-type dopant and the second p-type portion(s) including material doped with a p-type dopant, the second n-type portion(s) and the second p-type portion(s) being electrically coupled to one another via a second metal layer. The second n-type portion(s) may include a third n-type layer including material doped with the n-type dopant and a fourth n-type layer including material doped with the n-type dopant, the fourth n-type layer being electrically coupled to the third n-type layer by the second metal layer. Each of the first and second ohmic values may be selected in the range between about 30 xcexa9 and about 90 xcexa9. The integrated circuitry may implement an ATA Ultra DMA protocol and each of the first and second integrated circuit resistive elements may include one or more portions doped with an n-type dopant and one or more other portions doped with a p-type dopant.
The present invention may also be viewed as an integrated circuit for a host-peripheral interface via which digital data are synchronously transmitted at a data rate via conductive paths that exhibit transmission-line characteristics at the data rate. The integrated circuit comprises a first integrated-circuit terminal and a first connector terminal, a first transmission line for transmission of a data signal, a second integrated-circuit terminal and a second connector terminal and a second transmission line for transmission of a clocking signal. A first digital circuit propagates the data signal through a first pad and a second digital circuit propagates the clocking signal through a second pad. The first transmission line includes a first integrated-circuit conductive path including a first integrated-circuit resistive element connected in series between the first pad and the first digital circuit, and the second transmission line includes a second integrated-circuit conductive path including a second integrated-circuit resistive element The first integrated-circuit element has a first ohmic value and the second integrated-circuit element has a second ohmic value, each of the first and second ohmic values being of a magnitude that substantially matches a characteristic impedance of the conductive paths at the data rate.
According to further embodiments, the magnitude of each of the first and second integrated circuit resistive elements may be selected between about half and about double the characteristic impedance of the conductive paths at the data rate. The first integrated resistive element may include one or more first n-type portions and one or more first p-type portions, the first n-type portion(s) including material doped with an n-type dopant and the first p-type portion(s) including material doped with a p-type dopant, the first n-type portion(s) and the first p-type portion(s) being electrically coupled to one another via a first metal layer. The first n-type portion(s) may include a first n-type layer including material doped with the n-type dopant and a second n-type layer including material doped with the n-type dopant, the second n-type layer being electrically coupled to the first n-type layer by the first metal layer. The second integrated resistive element may include one or more second n-type portions and one or more second p-type portions, the second n-type portion(s) including material doped with an n-type dopant and the second p-type portion(s) including material doped with a p-type dopant, the second n-type portion(s) and the second p-type portion(s) being electrically coupled to one another via a second metal layer. The second n-type portion(s) may include a third n-type layer including material doped with the n-type dopant and a fourth n-type layer including material doped with the n-type dopant, the fourth n-type layer being electrically coupled to the third n-type layer by the second metal layer. Each of the first and second ohmic values may be selected in the range between about 30 xcexa9and about 90 xcexa9. The integrated circuit may implement an ATA Ultra DMA protocol and each of the first and second integrated circuit resistive elements may include one or more portions doped with an n-type dopant and one or more other portions doped with a p-type dopant.
The present invention may also be viewed as a printed circuit board assembly comprising an integrated-circuit terminal and a connector terminal, a printed-circuit conductive path connecting the integrated circuit terminal and the connector terminal, and integrated circuitry. The integrated circuitry includes a pad, a digital circuit for propagating the signal through the pad and an integrated-circuit conductive path connecting the pad to the integrated circuit terminal. The integrated circuit conductive path includes an integrated-circuit resistive element connected in series between the pad and the digital circuit, the integrated-circuit resistive element including one or more first portions doped with an n-type dopant electrically coupled to and separated from one or more second portions doped with a p-type dopant.
The first portion(s) doped with the n-type dopant may include a first n-type layer including material doped with the n-type dopant and a second n-type layer including material doped with the n-type dopant, the second n-type layer being electrically coupled with first n-type layer via a metal layer.
In another aspect the invention may be regarded as a source-synchronous driver circuit embedded in an integrated circuit chip. The source synchronous circuit comprises a first driver for transmitting a data signal; a first resistive element being connected in series between the first driver and a first pad; a second driver for transmitting a strobe signal simultaneously with the data signal to indicate validity of the data signal; and a second resistive element being connected in series between the second driver and a second pad The second pad is connected to a second pin for connecting the strobe signal to a second printed circuit board trace.
The foregoing and other features of the invention are described in detail below and set forth in the appended claims.